`timescale 1ns/1ns
module uart_rx_test;
  reg clk,rst,hl_sig,Rx_pin_in,Rx_en,bps_clk;
  wire count_sig,end_sig;
  wire[7:0] rx_data;
  rx u1(clk,rst,hl_sig,Rx_pin_in,bps_clk,Rx_en,count_sig,rx_data,end_sig);
  initial
  begin
    clk=1;rst=0;hl_sig=0;Rx_pin_in=0;Rx_en=0;bps_clk=0;
    #10 rst=1;hl_sig=1;Rx_en=1;
    #10 
    #10 bps_clk=1;
    #10 Rx_pin_in=1;
    #10 Rx_pin_in=1;
    #10 Rx_pin_in=0; 
    #10 Rx_pin_in=1;
    #10 Rx_pin_in=0;
    #10 Rx_pin_in=0;
    #10 Rx_pin_in=1;
    #10 Rx_pin_in=1;
    #10 bps_clk=1;
    #10
    #100 $stop;
  end
  always #5 clk=~clk;
  initial $monitor($time, , ,"clk=%b rst=%b hl_sig=%b Rx_pin_in=%b bps_clk=%b Rx_en=%b count_sig=%b rx_data=%b end_sig",clk,rst,hl_sig,Rx_pin_in,bps_clk,Rx_en,count_sig,rx_data,end_sig);
endmodule